Package ch.hevs.kart
Class KartRegisters.V1.Control.DrivePwmPeriod
java.lang.Object
ch.hevs.kart.KartRegisters.V1.Control.DrivePwmPeriod
- Enclosing class:
KartRegisters.V1.Control
The Drive PWM period as 16 bit unsigned integer (UINT16, 0..65535).
Value the FPGA main clock frequency is divided before used as base clock of the PWM step frequency. Default value is 0x40 = 64. For a value of 64 the FPGA clock will be divided by 64.
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Field Summary
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Constructor Summary
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Method Summary
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Field Details
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ADDRESS
public static final int ADDRESS- See Also:
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MIN
public static final int MIN- See Also:
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MAX
public static final int MAX- See Also:
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Constructor Details
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DrivePwmPeriod
public DrivePwmPeriod()
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Method Details
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FROM_HZ
public static int FROM_HZ(double frequency) -
TO_HZ
public static double TO_HZ(int registerValue)
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